A sample-and-hold circuit used in a liquid crystal display device is generally constructed by bi-polar transistors. Recently, the sample-and-hold circuit used in this field is required to operate at a lower voltage, such that it is necessary to simplify the circuit configuration and, in particular, to reduce the number of straightly stacked stages of transistors to enable low-voltage operation.
FIG. 2 shows an illustrative circuit configuration of this type of the conventional sample-and-hold circuit. Referring to FIG. 2, an input voltage Vin is entered to bases of transistors Q1, Q2 so that current flows through transistors Q5, Q1, Q3; Q2, Q7 and Q4 by sample clocks VCKH and VCKL entered to bases of transistors Q5 and Q7 to accumulate a voltage equal to the input voltage Vin in a holding capacitor C1.
Thus, the potentials VN1, VN2 of nodes N1, N2 are represented as EQU V.sub.N1 =Vin-VF EQU V.sub.N2 =Vin+VF
respectively. In the above equation, VF denotes a forward base-emitter voltage.
The voltage Vin accumulated in the holding capacitor C1 is outputted via a voltage follower A1.
During holding, sample clocks VCKH and VCKL become higher or lower than reference voltage sources VRH and VRL entered to opposite ends of differential transistor pairs to turn off transistors Q5, Q7 so that the current ceases to flow through the transistors Q1, Q2, Q3 and Q4.
Thus, the current is supplied from current sources I3 and I4 to transistors Q9 and Q10 such that the potentials V.sub.N1, V.sub.N2 of the nodes N1, N2 become EQU V.sub.N1 =Vin+VF EQU V.sub.N2 =Vin-VF
so that the base-to-emitter current paths of the transistors Q3 and Q4 are reverse-biased by 2 VF.
This holds charges accumulated in the holding capacitor C1 unchanged because the transistors Q3 and Q4 are completely cut off.